There are many types of memory circuits, such as static read access memory (SRAM), dynamic read access memory (DRAM), electrically erasable read only memory (EEPROM), flash memory, and other types of memory circuits. These memory circuits typically comprise a plurality of memory cells organized in a two-dimensional array. The memory cells are accessed by way of parallel word lines extending along one dimension (e.g., along the rows) of the memory array, and bit lines extending along an orthogonal dimension (e.g., along the columns) of the memory array. A particular memory cell is typically accessed by activating or applying a particular voltage to a word line coupled to that cell, and sensing a response from or applying another particular voltage to a bit line coupled to that cell.
Generally, an address predecoder is provided with the memory array for accessing one or more memory cells that correspond to an input binary address. More specifically, the address predecoder, via a row decoder in the memory array, activates the word line of the one or more memory cells corresponding to the input binary address. Usually, the predecoder receives the input binary address in an asynchronous manner, and activates the appropriate word line in a synchronous manner typically using a latch circuit responsive to a clock. After activating the particular word line for a defined time interval to allow access to the corresponding one or more memory cells, a reset signal is generated to reset the latch circuit and ensure that the particular word line is no longer activated.
In some cases, upon powering on such memory circuits, one or more latch circuits in the address predecoder may start up at the wrong state causing one or more word lines to be activated. The activated word lines may produce undesirable high currents in the memory array and may cause the memory circuit to operate in an abnormal manner. Thus, it would be desirable to generate a power on reset of the predecoder latches in order to prevent premature activation of word lines and prevent high currents and abnormal operations in the memory circuits.